1. Field of the Invention
The present invention refers to a multi-standard transmitter.
The invention concerns in particular, but not exclusively, a multi-standard transmitter for telecommunication systems and the following description refers to this field of application with the sole purpose of making it easier to explain.
2. Description of the Related Art
As well known, the configuration of interfacing devices or interfaces is one of the most critical parameters that influence the transfer of data with high performance.
The ability to interchange between different types of interface is indeed to this day a challenge that often influences the schedules linked to the configuration of devices using such interfaces and to their actual distribution onto the markets.
In particular, in making high-speed telecommunication systems, differential interfaces have become popular, like interfaces LVDS (acronym for: “Low-Voltage Differential Signalling”), LVPECL (acronym for: “Low-Voltage Positive Emitter-Coupled Logic”) and CML (acronym for: “Current-Mode Logic”). The success of such differential interfaces is linked to their ability to tolerate common-mode noise.
In any case, the transition between different types of interface used in transmitters and receivers of such telecommunication systems is problematic, should the technological differences between them not be taken into due consideration.
To better understand such technological differences, hereafter the basic characteristics of transmitters using known differential interfaces shall be described in greater detail.
A transmitter with LVDS interface or LVDS transmitter, as defined by standard IEEE1596.3, is a device made with low-voltage differential technology and with low power level, primarily intended for point-to-point data communication. Compared to other standard differential devices with cabled control, the LVDS transmitter has a minimum differential voltage oscillating in an admissible range of 250-400 mV with an offset value of 1.2Volt above a ground value.
Such an LVDS transmitter is schematically shown in FIG. 1, wholly indicated with 1.
The LVDS transmitter 1 essentially comprises a differential stage 2 with MOS transistors connected to a first and to a second voltage reference, in particular a VCC supply voltage reference and a ground GND, at a first X1 and a second inner circuit node X2 through a first MP and a second transistor MN, respectively, in particular a P channel MOS transistor and an N channel MOS transistor having the function of current generators.
The differential stage 2 has a pair of input terminals, IN+ and IN−, receiving respective complementary input signals, A_SW and AN_SW, as well as a pair of output terminals, OUT+ and OUT−, suitable for providing respective complementary output signals, VO and VON.
In greater detail, the differential stage 2 comprises a first M1 and a second transistor M2 inserted, in series with each other, between the first X1 and the second inner circuit node X2 and having respective control terminals connected together and to the first input terminal IN+ of the differential stage 2. Such first M1 and second transistors M2 are interconnected at the first output terminal OUT+ of the differential stage 2.
Similarly, the differential stage 2 comprises a third M3 and a fourth transistor M4 inserted, in series with each other, between the first X1 and the second inner circuit node X2 and having respective control terminals connected together and to the second input terminal IN− of the differential stage 2. Such third M3 and fourth transistors M4 are interconnected at the second output terminal OUT− of the differential stage 2.
Finally, the differential stage 2 comprises a resistive end element Rc, inserted between the first OUT+ and the second output terminal OUT−.
The transistors MP and MN having the function of current generators finally have control terminals receiving respective bias voltages PBIAS and NBIAS.
Substantially, the LVDS transmitter 1 makes a balanced current source, the output terminals of which, OUT+ and OUT−, provide voltage signals VO and VON, respectively positive and negative and phase-shifted of 180°.
In a telecommunications system, a receiver connected to such output terminals OUT+, OUT− detects a differential voltage capable of providing a logic signal. The resistive end element Rc allows the output terminals OUT+ and OUT− of the LVDS transmitter 1 to adapt to the different impedance values of a transmission line of the telecommunications system in which the transmitter is inserted, optimizing the integrity of a signal thus transmitted.
It should be remembered that an LVDS transmitter 1 as described above is able to interface with receiver circuits made in other differential technologies, provided that the signal levels used by such receiver circuits are within the preset common mode range, in other words between 0 and 2.4V.
An LVPECL transmitter essentially comprises a logic stage with coupled positive emitter having low power supply, typically below 3.3V, as defined for example by the standard Jedec8-2. In particular, the LVPECL transmitter has a variable output signal within a range equal to 600-900 mV.
Such an LVPECL transmitter is schematically shown in FIG. 2, wholly indicated with 3.
The LVPECL transmitter 3 comprises an input stage 4 inserted between a first and a second voltage reference, in particular a supply voltage reference Vcc and a ground GND, and connected to a first IN− and to a second input terminal IN+ of the LVPECL transmitter 3.
In particular, the input stage 4 comprises a first T1 and a second transistor T2, of the bipolar type having respective emitter terminals connected together, at an inner circuit node Yp, and to the ground GND through a generator Gp, respective emitter terminals connected, at a first Y1 and a second intermediate circuit node Y2, to respective first R1 and second resistive elements R2, in turn connected to the supply voltage reference Vcc, as well as command or base terminals respectively connected to the first IN− and to the second input terminal IN+ of the LVPECL transmitter 3.
The LVPECL transmitter 3 also comprises a third transistor T3 inserted between the supply voltage reference Vcc and a first output terminal OUT− of the LVPECL transmitter 3 and having a control or base terminal connected to the first intermediate circuit node Y1. Similarly, the LVPECL transmitter 3 also comprises a fourth transistor T4 inserted between the supply voltage reference Vcc and a second output terminal OUT+ of the LVPECL transmitter 3 and having a control or base terminal connected to the second intermediate circuit node Y2.
Finally, the output terminals OUT− and OUT+ of the LVPECL transmitter 3 are connected to a further supply voltage reference Vdd, respectively through a third R3 and a fourth resistive element R4, such resistive elements constituting an appropriate end for the LVPECL transmitter 3 in normal operating conditions (DC connection).
It should be noted that the structure shown for the LVPECL transmitter 3 has a low output impedance, and therefore does not carry out a correct impedance adaptation when a long transmission line is driven.
A CML transmitter essentially comprising a current switching output buffer is schematically shown in FIG. 3 and wholly indicated with 5.
The CML transmitter 5 comprises a first T1 and a second transistor T2, having respective emitter terminals connected together, at an inner circuit node Yp, and to a voltage reference, in particular a ground GND, through a generator Gp, respective emitter terminals connected to respective first R1 and second resistive element R2, in turn connected to a further voltage reference, in particular the supply voltage reference Vcc, as well as command or base terminals respectively connected to a first IN− and to a second input terminal IN+ of the CML transmitter 5.
The emitter terminal of the second transistor T2 is connected to a first output terminal OUT− of the CML transmitter 5, whereas the emitter terminal of the first transistor T1 is connected to the second output terminal OUT+ of the CML transmitter 5.
Typically, the CML transmitter 5 uses resistive elements of a value equal to 50 Ω for an optimal integrity of a transmitted signal.
Indeed, in a telecommunications system, on the receiver side, there is typically an end element with a resistive value equal to 50 Ω that make a current switch equal to 400 mV on the driver side.
It should be noted that the common mode voltage of the CML transmitter can be taken to the supply voltage value Vcc or to the value of the ground GND, but normally it is taken to a value slightly lower than the supply voltage (typically Vcc−0.2V).
Transmitters are also known that respect the standard CPRI, biased at a nominal current that is double CML, having common mode voltage values corresponding to the supply voltage value Vcc decreased by 0.4V.
In telecommunication systems, it is known to use substantially two interface modes between LVDS, LVPECL and CML type transmitters, and in particular the methods of:
1. DC coupling;
2. AC coupling
respectively schematically shown in FIGS. 4A and 4B.
The DC coupling method uses substantially a DC translation resistive network 6, as shown in FIG. 4A. According to the relationship between the interfaces included in the receiver and in the transmitter within the common mode range, the common mode voltage of such interfaces in contact through the resistive network 6 can be stepped up or stepped down.
In particular it is known to use a Therein resistive network analysis method to make an interconnection with DC coupling. For example, to place a LVPECL type transmitter in communication with an LVDS receiver, which requires a lower common mode voltage than the LVPECL transmitter, a step-down resistive network is used to reduce the common mode voltage, typically from Vcc−1.3V to 1.2V.
It can immediately be seen that the introduction of the resistive network 6 results in additional occupation of area and an increase in consumption of the telecommunication system overall. Moreover, such a solution with DC coupling does not have any configurability, it increases the attenuation of the signals, increases the costs of the printed board in which receiver and transmitter are made, lowers the yield of the telecommunication system and makes routing difficult on the printed board.
The AC coupling method, on the other hand, foresees the use of integrated buffer/translator circuits 7, as shown in FIG. 4B.
Such an integrated solution is also not without drawbacks, in particular low configurability, increased consumption, high cost of the printed board in which receiver and transmitter are made, lowering of the yield of the telecommunication system and difficult routing on the printed board.